[llvm-dev] POssible bug in the Arm code generator

[Owen Shepherd via llvm-dev]

Pay closer attention to the instruction descriptions on the page you linked
above:

LDR{*type*}{*cond*} *Rt*, [*Rn* {, #*offset*}]        ; immediate offset

LDR{*type*}{*cond*} *Rt*, [*Rn*, #*offset*]!          ; pre-indexed


The pre-indexed form is always specified with an offset, and* follows the
brackets with an exclamation mark*. You have an immediate offset load, for
which Rt==Rn is permitted.

A possible reason for an illegal instruction exception is that you have
generated some ARM code and tried to execute it as Thumb or vise-versa.

On Sun, Sep 6, 2015 at 5:40 AM Erik de Castro Lopo via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hi all,
>
> I do a little work on the Glasgow Haskell Compiler (GHC) which uses
> LLVM for the backend when compiling for Arm and some other targets.
>
> The reason I am posting to this list is that a GHC compiled program
> (using the LLVM backend) is getting an illegal instruction exception
> on the this instruction:
>
>      ldr     r0, [r0]
>
> According to the Arm archtecture manual:
>
>
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489i/CIHGJHED.html
>
> this is pre-indexed load instruction of the form:
>
>     LDR{type}{cond} Rt, [Rn, #offset]
>
> but is illegal because the pre-indexed form of this instruction does
> not allow 'Rt' and 'Rn' to be the same register.
>
> The above all makes sense, but I find it a little hard to believe that
> I am the first person to find this.
>
> I'm using llvm-3.6.2 from a Debian package.
>
> Clues? Comments?
>
> Cheers,
> Erik
> --
> ----------------------------------------------------------------------
> Erik de Castro Lopo
> http://www.mega-nerd.com/
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