[llvm-dev] [AMDGPU] AMDGPUAsmParser fails to parse several instructions

李弘宇 via llvm-dev llvm-dev at lists.llvm.org
Fri Oct 23 00:36:09 PDT 2015

Dear Developers,

I compile a OpenCL kernel, FFT, in AMDAPP SDK v2.5 using clang 3.8 + libclc
and assembling the code with lld (The LLVM linker). The assembly code
contains the following assembly codes (and lots of other similar format
assembly) that fails to be parsed by AMDGPUAsmParser. It seems to me that
both are valid instructions after looking at the SI instruction spec.

s_mov_b32 s0, 0xfe5163ab
v_mad_f32 v9, 0.5, v5, -v8

To reproduce this, I write this two lines in a text file and run

llvm-mc -arch=amdgcn -mcpu=kaveri input.s

The first line has the following error message:

sop1-playground.s:1:15: error: invalid immediate: only 32-bit values are
s_mov_b32 s0, 0xfe5163ab
sop1-playground.s:1:25: error: failed parsing operand.
s_mov_b32 s0, 0xfe5163ab
The part of stack dump:

#9 0x4711ee (anonymous namespace)::AMDGPUOperand::setModifiers(unsigned
#10 0x46ff6a (anonymous
std::default_delete<llvm::MCParsedAsmOperand> > >&, llvm::StringRef)
#11 0x46cd46 (anonymous
llvm::StringRef, llvm::SMLoc,
std::default_delete<llvm::MCParsedAsmOperand> > >&)

The second line of the assembly has the assertion fail:

void (anonymous namespace)::AMDGPUOperand::setModifiers(unsigned int):
Assertion `isReg()' failed.

and reports that 0.5 is "error: invalid operand for instruction"

v_mad_f32 v9, 0.5, v5, -v8


李弘宇 (Li, Hong-Yu)
Department of Computer Science & Information Engineering
National Taiwan University
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