[llvm-dev] Instructions with no operand

Sky Flyer via llvm-dev llvm-dev at lists.llvm.org
Mon Oct 19 08:04:50 PDT 2015

Hi all,

I am trying to implement an instruction with no operand for example "clr"
in TableGen.



class TestInst<string opc, string asmstr, dag oops, dag iops,
                list<dag> pattern> : Instruction { ... }

def int_no_operand : Intrinsic<[]>;
class ALU<string opc> : TestInst<opc, "", (outs), (ins),

multiclass Clr {
 def _ : ALU<"clr">
   {let InstOp  = 0b11;}


after compiling the code, I receive the following error:

*llvm-tblgen: /llvm/utils/TableGen/CodeGenInstruction.h:186:
std::pair<unsigned int, unsigned int>
llvm::CGIOperandList::getSubOperandNumber(unsigned int) const: Assertion `i
< OperandList.size() && "Invalid flat operand #"' failed.*

How can I define an instruction with no operand?
In ARM there is a similar instruction like "CLREX" but I don't understand
why in the assertion in CodeGenInstruction.h number of sub operand num
should be more than 0? getSubOperandNumber counts the operator (i.e. the
instruction mnemonic itself) as well? I mean, we will have minimum 1 in any
situation or it's just the number of operators?!

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151019/26d8de7d/attachment.html>

More information about the llvm-dev mailing list