[LLVMdev] [PATCH][RFC] HSAIL Target
Matthew.Arsenault at amd.com
Fri May 15 16:21:54 PDT 2015
> On May 15, 2015, at 4:00 PM, Reid Kleckner <rnk at google.com> wrote:
> Can you provide some high-level statistics on the amount of code involved in the various pieces? It's a crude approximation of how complex the pieces (backend, assembler, disassembler) are.
There is no assembler, inline assembly support or disassembler support and no current plan to implement those. The backend is all there is, and I think it’s pretty similar in size to other targets at this time. The parts I’ve spent the most time on and were the most problematic were for the required pretty printing of various components, so most of the complexity of the backend is really for printing purposes.
> If HSAIL is similar to AMDIL and NVPTX, how does it compare to SPIR-V? Is it more of a backend, with lots of lowering, or more of a portable program representation?
It’s a replacement for AMDIL. It is a virtual ISA, with physical registers and mostly goes through the normal target code generation paths. It is not similar in design to SPIR-V, although its purpose is pretty similar.
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