[LLVMdev] Why change "sub x, 5" to "add x, -5" ?

[Krzysztof Parzyszek]

Other people can elaborate on that, but the general idea is to transform 
functionally equivalent programs into the same internal representation. 
  In this case, the desired representation is "add-immediate" for 
instructions that are equivalent to it.

Target-specific selection patterns can deal with it by having predicates 
that accept or reject the pattern depending on specific values in the 
DAG: in case of your ISA they could reject the "add" pattern in favor of 
the "sub" pattern when the immediate is negative.

-Krzysztof


On 7/8/2015 10:00 AM, Frédéric Heitzmann wrote:
> Dear all,
>
> I have been working on a new LLVM backend. Some instructions, like sub,
> can take an positive constante, encoded into 5 bits thus lower than 32,
> and a register, as operands.
> Unfortunately, DAGCombiner.cpp changes patterns like 'sub x, 5' into
> 'add x,-5'.
>
> Similarly, I found changes in some IR to IR passes, with no clear gain
> (at least not clear to me), and even penalty for my specific ISA.
>
> %add = add i32 %a, %b
> %tobool = icmp eq i32 %add, 0
>
> becomes :
>
> %add = sub i32 0, %b
> %tobool = icmp eq i32 %a, %
>
> My question is not how to workaround those, but why such changes are
> done for all targets, in DAG selection or in IR passes.
> AFAIK, there is no target which has some better encoding with a negative
> value than with a positive one.
> And "sub" looks as costly as "add" to me.
>
> Is there some other practical reason to perform this kind of change ?
> Thanks for your highlights.
>
> --
> Frederic Heitzmann
>
>
>
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