[LLVMdev] Match immediate value in tablegen

[Xiaochu Liu]

It works now after I changed it to :
def: Pat<(v2i16 (build_vector i16:$src1, i16:$src2)), (OR (SLLI GPR:
$src1,16), GPR:$src2>;
I guess it's because I messed up with operand type for build_vector
previously.
Thanks Matt!

On Wed, Jul 1, 2015 at 2:25 PM Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:

> On 07/01/2015 02:06 PM, Xiaochu Liu wrote:
>
> I was trying to do a pattern matching for a rd+imm instruction in my own
> backend.
> It looks something like:
> def: Pat<build_vector v2i16:$src1, v2i16:$src2, (OR (SLLI GPR: $src1,16),
> GPR:$src2>;
> OR takes two i32 in registers and SLLI takes one i32 in registers and an
> immediate.
>
>  But the immediate '16' does not work here and I tried different ways.
> May I know if any of you have any idea how to bake an immediate value (16)
> into the tablegen?
>
>
>
> How specifically doesn't it work / what is the error? What version of LLVM
> are you using?How are SLLI's operands defined?
>
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