[LLVMdev] How to specify displacement range of a target instruction to llc

[Ziqiang Patrick Huang]

Thanks, I found the bug.

2015-02-20 8:21 GMT-05:00 Anton Korobeynikov <anton at korobeynikov.info>:

> You'd need to ask the authors of this backend, not here.
>
> On Thu, Feb 19, 2015 at 7:48 PM, Ziqiang Patrick Huang
> <ziqiang.huang1001 at gmail.com> wrote:
> > Any help ???
> >
> > 2015-02-18 13:43 GMT-05:00 Ziqiang Patrick Huang
> > <ziqiang.huang1001 at gmail.com>:
> >
> >> Hi,
> >>
> >> I'm working on a project that use llvm openrisc beckend (currently not
> >> part of the upstream). Right now I'm looking at a bug where llc
> generates
> >> memory instructions that has out-of-range displacement, for example
> >>
> >> l.sb 37668(r1), r2    in which 37668 is a 17 bit signed integer, but
> the
> >> instruction only allows 16 bit signed displacement. As a result, after
> >> running through the assembler, 37668 is encoded wrongly into -27668
> because
> >> it's being sign extended.
> >>
> >> Can someone point to me where should I add code to do the check, any
> API I
> >> can use ?
> >>
> >> Thanks,
> >> Patrick
> >
> >
> >
> >
> > --
> > Ziqiang Huang
> > Electrical and Computer Engineering
> > Hudson 213c, Duke University
> > Tel: 919-491-3677
> > Email: ziqiang.huang at duke.edu
> >
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
> >
>
>
>
> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>



-- 
*Ziqiang Huang*
*Electrical and Computer Engineering*
*Hudson 213c, Duke University*
*Tel: 919-491-3677*
*Email: ziqiang.huang at duke.edu <ziqiang.huang at duke.edu>*
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