[llvm-dev] llvm-3.6 MCAsmParser x64 Error "invalid operand for instruction" when msb set

[Garba, Peter via llvm-dev]

Hi Roman,

in the mode you want to use the opcodes both immediate are defined as signed values.

Imm32 is defined in the range −2.147.483.648 to 2.147.483.647

In your case 0x80000000 will interpreted by the assembler as the unsigned value 2.147.483.648 which is bigger than 2.147.483.647

If you want to assemble that specific Imm in hex representation then you have to assemble:

“add rax, 0x80000000” as “add rax, -2147483648”
“add rax, 0xfffffffff” as “add rax, -1”
“imul rbx, rsi, 0x80000000” as “imul rbx, rsi, -2147483648”
“imul rbx, rsi, 0xffffffff” as “imul rbx, rsi, 0xffffffff”

Best regards,
Peter Garba


>From the Intel Manuel:
ADD r/m64, imm32 MI Valid N.E. Add imm32 sign-extended to 64-bits to r/m64.

IMUL—Signed Multiply:
IMUL r32, r/m32, imm32 RMI Valid Valid doubleword register ← r/m32 ∗ immediate doubleword.


From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Rohleder, Roman (Contractor) via llvm-dev
Sent: Donnerstag, 17. Dezember 2015 11:15
To: llvm-dev at lists.llvm.org
Subject: [llvm-dev] llvm-3.6 MCAsmParser x64 Error "invalid operand for instruction" when msb set

Hello,

I am experiencing problems, when trying to assemble these two x86-64 Opcodes
“add r64, imm32”
“imul r64, r64, imm32”

When having the most significant bit set for imm32, for example:
“add rax, 0x80000000”, “add rax, 0xffffffff”, …
“imul rbx, rsi, 0x80000000”, “imul rbx, rsi, 0xffffffff”, …

The Error Message I receive is the following:
„Instruction:1:1: error: invalid operand for instruction“

I was using the MCAsmParser, with the RelaxAll Flag set to true, for the MCStreamer.

Can someone clarify, as to why this is happening, or what I am missing?
Thank you in advance.

Kind regards
Roman



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Company Registration number: Amtsgericht Muenchen HRB 171025
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