[llvm-dev] Allowing virtual registers after register allocation

Quentin Colombet via llvm-dev llvm-dev at lists.llvm.org
Thu Dec 10 12:03:09 PST 2015

> On Dec 10, 2015, at 11:21 AM, Derek Schuff <dschuff at google.com> wrote:
> On Thu, Dec 10, 2015 at 11:13 AM Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote:
> > I don’t know for the other passes, but I don’t think it makes sense
> > to teach PrologEpilogInserter to work on virtual registers, since
> > part of its job is to get rid of any virtual registers created when
> > lowering the frame.
> > I.e., that would indirectly mean that we would need to teach the
> > scavenger how to recycle virtual registers!
> >
> I think this is exactly the part of PEI that they disable.
> Yes; see  http://reviews.llvm.org/D15394 <http://reviews.llvm.org/D15394>
> If the target has no callee-saved registers and you disable scavenging, you're basically left with.... prolog/epilog insertion and FrameIndex elimination.

I can’t shake the feeling that this is a hack.
After RA we shouldn’t have virtual registers anymore. I would even be in favor for a change in the verifier to complain about that.

My concern, aside the semantic aspect, is that we will have such patches all over the place and that the coverage will be very low.

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