[llvm-dev] MISched: latency of function-live-in registers?
Johnson, Nicholas Paul via llvm-dev
llvm-dev at lists.llvm.org
Tue Dec 8 12:47:32 PST 2015
I use the machine scheduler with my out-of-tree backend.
Is it possible to tell the machine scheduler that certain function-live-in physical registers (i.e., function arguments) have a non-zero latency?
Said another way, I want to indicate to the scheduler that certain physical registers are not available at the beginning of the function's entry block and that attempting to access those registers will incur a stall.
D. E. Shaw Research
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