[llvm-dev] Splitting 'expand' into 'split' and `expand`.
Dylan McKay via llvm-dev
llvm-dev at lists.llvm.org
Thu Aug 13 01:41:07 PDT 2015
It’s faked by saying 64-bit add is legal and the expand to add + carry is
handled during instruction selection, which works and also makes addressing
mode matching easier.
This is basically what we do currently. So this proposal (or at least
something similar) would also help the AMDGPU backend?
On Thu, Aug 13, 2015 at 4:21 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
> On Aug 12, 2015, at 8:36 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote:
> - 16-bit addition is illegal, should expand into an add and an add
> with carry
> - A few operations support 16-bit operands - the 16-bit DREGS register
> This sounds like basically the same situation AMDGPU has with 64-bit
> integers. Since you have a 16-bit register class, you avoid terrible
> problems by not having i16 be a legal type. There is no 64-bit add, and
> needs to be expanded into 32-bit add + carry. There are fewer 64-bit
> operations available, but some are. It’s faked by saying 64-bit add is
> legal and the expand to add + carry is handled during instruction
> selection, which works and also makes addressing mode matching easier.
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