[llvm-dev] ARM: Predicated returns considered analyzable?

Renato Golin via llvm-dev llvm-dev at lists.llvm.org
Tue Aug 11 06:32:08 PDT 2015

On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> -->     %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR,
> %R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>,
> %PC<imp-use,undef>
> Here the instruction t2LDMIA_RET is a terminator and yet it's followed by a
> non-terminator tBLXi.  This looks wrong.  Does anyone have any comments on
> this?

Isn't it because one of the predicates is CPSR, which means it's a
conditional instruction, so not really a terminator?

This lowers to the expected:

    str lr, [sp, #-4]!
    cmp r1, #0
    it ne
    cmpne r0, #3
    bhi .LBB0_2 <-- Turned into a conditional jump

    bl bar

    ldr lr, [sp], #4
    bx lr


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