[LLVMdev] RFC: Machine Level IR text-based serialization format

[Alex L]

2015-04-28 10:52 GMT-07:00 Krzysztof Parzyszek <kparzysz at codeaurora.org>:

> On 4/28/2015 12:46 PM, Alex L wrote:
>
>>
>> I hope that answers your question,
>>
>
> Partly. :)
> I'm wondering what support you would need from each target.  Obviously
> you'd need to be able to parse the mnemonics and the register names, but
> that's probably doable without additional target-specific support.
>

Yes, the mnemonics and register names should be fairly straight forward.

However, there are several target specific data structures that a machine
function might have, like the MachineFunctionInfo.
The MachineFunctionInfo is particularly interesting, as it can be difficult
to serialize on certain targets, like Mips, XCore and Hexagon,
but luckily the other targets have a pretty simple subclass of
MachineFunctionInfo. I think that each target's MachineFunctionInfo
and other similar classes would have to be extended to contain the
intrusive methods for serialization.

The instructions themselves don't have too many target specific stuff, but
they do have a couple of things. Although there are some
target specific things that don't even need to be serialized - like the
MipsCallEntry, which can be used in a MachineMemOperand,
but doesn't contain any data when LLVM is compiled in release mode.

Alex.


> Also, is this going to support SSA and post-SSA/post-RA code?


Yes, it's going to support both SSA and post SSA code.


>
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
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