[LLVMdev] Optimization on Atomics (and the OpenMP memory model)

[JF Bastien]

Architecture-specific NaCl basically uses whatever the underlying ISA
expects (so answers will be "same as the above"), save for any OS
interactions which go through NaCl's own syscalls (which then sometimes
punt to the host OS). The most interesting here is futex, which is a
restricted version of Linux' futex and gets emulated on non-Linux guests.

For PNaCl none of the C++ constructs get lowered past their C++ semantics
(they look like functions calls). futex is still a syscall for PNaCl. C++
constructs only get lowered once the actual ISA is known (translation time)
at which point we're usually generating NaCl code and the same as the above
applies.

The same as PNaCl would apply to JavaScript once it supports
SharedArrayBuffer if the current proposal goes forward. One small change
would be to rely on synchronic instead of futex.

I'm not familiar enough with taskwait, omp_set_lock / omp_unset_lock to
provide a useful answer. I assume that we can implement them with atomics
and futex if QOI isn't an issue?

On reordering: yes, as much as C++ allows. Good timing for this:

https://github.com/jfbastien/papers/blob/master/source/N4455.rst


On Fri, Apr 10, 2015 at 10:12 AM, Hal Finkel <hfinkel at anl.gov> wrote:

> Hi everyone,
>
> The OpenMP standards committee has begun work to formalize their memory
> model, and define its relationship to the C/C++ memory models. A
> questionnaire has been put together (pasted below), and I'd like everyone's
> help in composing detailed answers to inform their decision-making process.
> While our OpenMP support is still in active development, many of these
> questions apply equally to C/C++ atomics, and a lot of work has certainly
> been done here on that front.
>
> * Which processor architectures does your compiler target (e.g. x86,
> Power, ARM, ARM v8, Xeon Phi, Nvidia GPUs, etc.)?
>     [I'll just answer "yes" for that one ;)]
> * What is a flush lowered to in assembly for each of the supported
> architectures? For instance, a flush might be implemented as an MFENCE on
> the x86 architecture in some compilers.
> * What are non-seq_cst atomic read, write, update and capture lowered to
> for each of your targets?
> * What are seq_cst atomic read, write, update and capture lowered to for
> each of your targets?
> * What is the taskwait construct lowered to for each of your targets?
> * What are omp_set_lock and omp_unset_lock lowered to for each of your
> targets?
> * What is a barrier lowered to for each of your targets?
> * Are any optimisations allowed to reorder, change or remove code that
> uses any of the synchronisation constructs above, or any of the other
> synchronisation constructs in section 2.12 of the OpenMP 4.0 specification?
>
> I'll be happy to collate answers to send back to the committee; please
> provide as much feedback as you can.
>
> Thanks in advance,
> Hal
>
> --
> Hal Finkel
> Assistant Computational Scientist
> Leadership Computing Facility
> Argonne National Laboratory
>
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