[LLVMdev] Cast to SCEVAddRecExpr

[Sanjoy Das]

> Cases where we have power of two will be transformed to shift reduction by Instruction Combiner.
> i.e. var[i * 2] will be transformed to var[i << 1] but 'nsw' property was not carried forward.

That looks like an instcombine bug -- for anything except i2 (I assume
you're not indexing into an array using an i2) "mul nsw X, 2" should
be equivalent to "lshr nsw X, 1", irrespective on what is decided on
that thread.

> (sext i32 Addrec{2,+,2}<nuw><%for.body4> to i64)

Do you mean (sext i32 Addrec{2,+,2}<nsw><%for.body4> to i64)?  If so, then yes.

>
> Transformed To:
> Addrec{(sext i32 '2' to i64), + , (sext i32 '2' to i64)} <nsw><%for.body4>

-- Sanjoy