[LLVMdev] Behaviour of NVPTX intrinsic

[Jonathan Roelofs]

Have a look at how the ARM backend handles the CPSR register. It sounds like
what you're really looking for is liveness of that status register not to be
clobbered between the arithmetic instruction you're inspecting and the
instruction that reads that register.


Cheers,

Jon

On 9/30/14 12:39 PM, Jingyue Wu wrote:
> I can't think of any NVPTX intrinsic that disallow even arithmetic
> instructions.
> 
> If you are trying to read some special registers in PTX, can you use inline
> assembly and mark it as having side effects? I think LLVM's optimizer is
> very conservative about inline assembly marked with sideeffect, and will
> probably solve your code motion issue.
> 
> Jingyue
> 
> On Tue Sep 30 2014 at 11:03:45 AM RAVI KORSA <ravi.korsa at gmail.com> wrote:
> 
>> The actual purpose that I wanted such an intrinsic is to solve a problem
>> similar to this one in X86. Say I wanted to read the "mxcsr" register(which
>> is the status register for SSE instructions) after a particular
>> instruction, then I need a kind of barrier intrinsic which will not allow
>> the arithmetic instructions to move around it. Or else I will be reading
>> the status of some other instruction.
>>
>> Thanks
>>
>
> 
> 
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