[LLVMdev] Adding masked vector load and store intrinsics

dag at cray.com dag at cray.com
Tue Oct 28 09:34:50 PDT 2014

"Demikhovsky, Elena" <elena.demikhovsky at intel.com> writes:

>> But passthrough has to have some value, right, to know what to merge?
> [Demikhovsky, Elena] Not necessarily. It may be "undef" on IR
> level. When we don't care about value in masked-off lanes.

I was including "undef" as a "value."  :)

>> It must appear as an operand, correct? 
> [Demikhovsky, Elena] Yes.

Great, this sounds very good.


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