[LLVMdev] Masked vector intrinsics and name mangling

Demikhovsky, Elena elena.demikhovsky at intel.com
Sun Oct 26 03:34:46 PDT 2014


The proposed masked vector intrinsics are overloaded - one intrinsic ID for multiple types.
After name mangling it will look like:

%res = call <16 x i32> @llvm.masked.load.v16i32.p0i32.v16i32.i32.v16i1(i32* %addr, <16 x i32>%passthru, i32 4, <16 x i1> %mask)
6 types x 3 vector sizes = 18 names for one operation

I propose to remove name mangling from these intrinsics:
%res = call <16 x i32> @llvm.masked.load (i32* %addr, <16 x i32>%passthru, i32 4, <16 x i1> %mask)

  def int_masked_load :
      Intrinsic<[llvm_anyvector_ty], [llvm_anyptr_ty, llvm_anyvector_ty, llvm_anyint_ty, llvm_anyvector_ty],
                [IntrReadArgMem, NoNameMangling]>; // new property

It will significantly simplify reading and manual writing.
What do you think?

Thank you.

-        Elena

Intel Israel (74) Limited

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