[LLVMdev] Adding masked vector load and store intrinsics

[dag at cray.com]

Adam Nemet <anemet at apple.com> writes:

> I am particularly worried whether we really want to generate these for
> targets that don’t have vector predication support.

We almost certainly don't want to do that.  Clang or whatever is
generating LLVM IR will need to be aware of target vector capabilities.
Still, legalization needs to be available to handle this situation if it
arises.

> There is also the related question of vector predicating any other
> instruction beyond just loads and stores which AVX512 supports. This
> is probably a smaller gain but should probably be part of the plan as
> well.

It's not a small gain, it is a *critical* thing to do.  We have
customers that always run with traps enabled and without masking, it
severely limits what code can be vectorized.

                               -David