[LLVMdev] Adding masked vector load and store intrinsics

dag at cray.com dag at cray.com
Fri Oct 24 12:22:58 PDT 2014

"Smith, Kevin B" <kevin.b.smith at intel.com> writes:

>> So %passthrough can *only* be undef or zeroinitializer?
> No, that wasn't the intent.  %passthrough can be any other definition
> that is needed.  Zero and undef were simply two possible values that
> illustrated some interesting behavior.

> Mapping of the %passthrough to the actual semantics of many vector
> instruction sets where the masked instructions leave the masked-off
> elements of the destination unchanged is done in a similar manner as
> three-address instructions are turned into two address instructions,
> by placing a copy as necessary so that dest and passthrough are in the
> same register.

How would one express such semantics in LLVM IR with this intrinsic?  By
definition, %data anmd %passthrough are different IR virtual registers
and there are no copy instructions in LLVM IR.

In the more general case:

%b = call <8 x i32> @llvm.masked.load (i32* %addr, <8 x i32> %a, i32 4, <8 x i1> %mask)

where %a and %b have no relation to each other, I presume the backend
would be responsible for doing a select/merge after the load if the ISA
didn't directly support the merge as part of the load operation.  Right?


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