[LLVMdev] Isel DAG documentation?

[David Given]

On 3/9/14, 10:40 PM, David Given wrote:
> That seems
> sensible... but I'm afraid it doesn't work, dying in precisely the same
> way as above.

So I think I've reached the bottom of this.

It looks like the generated table loses type information. At one point I
had a rule that looked like this:

def MOVr : S16<
    (outs GR32:$rD), (ins GR32:$rS),
    "mov $rD, $rS",
    [(set GR32:$rD, GR32:$rS)]
>;

This ended up last on the opcode list, and was always invoked if no
other instruction matched --- because the selection pattern is basically
'x = y' from the point of view of the instruction selector, and
therefore fits everything.

I believe that the same thing's applying to the globaladdr issue. I had
rules that look like this:

> def MOVar : S32<
>   (outs GR32:$rD), (ins i32imm:$addr), // i32imm is wrong here
>   "mov $rD, $addr",
>   [(set GR32:$rD, tglobaladdr:$addr)]
>> ;
> def : Pat<(globaladdr:$addr), (MOVar tglobaladdr:$addr)>;

...but that (set) ends up as a rule which compiles to 'x = y' and
everything goes horribly wrong.

What I eventually did was to copy what the ARM target does: add code to
TargetLowering::LowerOperation() to explicitly convert the globaladdr
nodes into wrapped machine-specific nodes. My MOVar now looks like:

def MOVar : S32<
   (outs GR32:$rD), (ins i32imm:$addr), // i32imm is wrong here
   "mov $rD, $addr",
   [(set GR32:$rD, (WrappedGlobal tglobaladdr:$addr))]
>;

The WrappedGlobal has no semantic meaning, simply being a
machine-specific ISD node with a single parameter. I'm not quite sure
*why* this works; it is, after all, the failing rule above should do
precisely the same thing, but in a less cryptic way.

I suspect there's an llvm bug here, but I'm not quite sure what it is.
It would be nice if tablegen was a bit more rigorous about detecting
invalid patterns (is there an option I'm missing?).

-- 
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