[LLVMdev] initialize register attributes in instruction definition

[kewuzhang]

Hi All, 

Is it possible to initialize(set up)  register attributes when we define an instruction?

like  

if a register is defined like this:

" class SC_Register<bits<8> register_num, 
                   	 REG_FLAG  SC_X,
			 REG_FLAG  SC_Y,
			 REG_FLAG  SC_Z,
			 REG_FLAG  SC_W,
                  	 string asmstr> : Register<asmstr>
{
	
    	let HWEncoding{7-0}     = register_num;         // register_num
	let HWEncoding{8}     = SC_X;  
	let HWEncoding{9}     = SC_Y;  
…..
}”

can I set up the input/ouput register flags like this? or some other way in codegen to make the register flags are set up based on the instructions?

let Constraints = “$dst.SC_X =1, $src.SC_Y =0" in 
{
    def GENri : my_instr  <op,  0,   (outs GPR_V4_R32:$dst),  (ins GPR_V4_R32:$src),
                                      !strconcat(asmstr, " $dst, ""$src"), 
                                     [(set v4i32:$dst, (node v4i32:$src)]>;
                                       
}



tks


kevin
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140731/57ca8208/attachment.html>