[LLVMdev] need advice on approach for backend (llvm3.4.2)

[Richard Gorton]

Hi,

I'm working on a backend for a 64-bit RISC-like architecture; all registers are 64-bits.  I have load/store granularity of 8/16/32/64 bits (pretty normal stuff), but also 128-bit load/stores (involving a pair of registers).  Because all registers can be used in integer and float instructions, I only have a single register class (so far).

I'm trying to figure out a good way to utilize our 128-bit loads/stores - the data  can be in any two 64-bit registers, but the memory locations must be strongly aligned and adjacent (aka first register to 0mod16 address, 2nd register to 8mod16 address).  The stack is guaranteed to be 0mod16 aligned.

I was thinking of doing this coalescing in CogERgisterInfo::eliminateFrameIndex (Our target == 'CogE') but then spotted some code  re: register scavenging which could make this problematic.

I also see that there is ARM/ARMLoadStoreOptimizer.cpp, which performs a similar coalescence.


The two questions then:
1) for those of you who are working on retargeting the backend, what approach would you recommend that I use for this kind of coalescence?
2) What are the pitfalls I am likely to encounter?


Thanks in advance,

	Richard Gorton
	Cognitive Electronics
	www.cog-e.com