[LLVMdev] A problem about Anti-Dependence breaker when compiling for ARM

[Anthony Yu]

Hello everyone,

I enable post RA scheduler and anti-dependence breaker for the ARM
back-end. However, the breaker generates the wrong code, which doesn't put
return value in the first register w0. The breaker rename the w0 by other
register in the function tail. Do I miss out some things to let it function
correct? I would appreciate any ideas.

Anthony Yu

=====
The following is the sample llvm-IR and part of assembly code compiled by
llc. I enable aggressive anti-dependence breaker.

===  sample LLVM-IR
@lhs = global fp128 zeroinitializer, align 16
@rhs = global fp128 zeroinitializer, align 16
define i32 @test() {
  %lhs = load fp128* @lhs, align 16
  %rhs = load fp128* @rhs, align 16
  %val = fcmp ugt fp128 %lhs, %rhs
  %tt = select i1 %val, i32 5, i32 6
  ret i32 %tt
}
===

=== part of assembly code compiled by llc ARM back-end
...
    bl  __unordtf2
    cmp  w0, #0                 // =0
    movz    w20, #0x5
    cset     w8, ne
    orr  w8, w8, w19
    cmp  w8, #0                 // =0
    cinc     w30, w20, eq     //   write to w0 when compiling without the
breaker
    sub sp, x29, #16            // =16
    ldp x29, x30, [sp, #16]
                                                            ldp x20, x19,
[sp], #32
    ret
...
===
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