[LLVMdev] Why make the register list a dag for RegisterClass in target descriptor file?
t.p.northover at gmail.com
Sun Jan 19 03:57:24 PST 2014
On 19 January 2014 10:19, Thomson <lilotom at gmail.com> wrote:
> The blow snippet in target.td shows the regList in RegisterClass is typed as
> dag. Why not make it a simple list, such as list<Register>?
I don't know about the original reason, but these days we have a few
operators in use to make constructing those sets easier which would be
much harder to do for lists. E.g. "(sequence "R%u", 0, 12)", "(sub
GPR, PC)" from ARM.
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