[LLVMdev] How to implement register allocation constraints to guide allocator dispatching different registers for certain instruction?
kevinqindev at gmail.com
Wed Feb 19 01:09:44 PST 2014
To fix this bug(http://llvm.org/bugs/show_bug.cgi?id=18881), we need to add
more register constraints that for STLXR , Ws and Wt should not be the same
register. Because these unpredictable instructions are valid instructions
in MC layer, we couldn't just simply treat them as unallocated encoding.
I suppose to add some extra rules on register allocator to avoid it
allocating register causing any unpredictable behavior, but I don't have
experience to this part. Can anybody tell me how to implement this or have
better ideas to solve this problem? Thanks in advance.
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