[LLVMdev] Question about per-operand machine model

[JinGu Kang]

Hi Andy and all,

I have a question about per-operand machine model. I am finding some 
relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'.

For example,

class InstTEST<..., InstrItinClass itin> : Instruction {
   let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>

// schedule info
II_TEST: InstrItinClass;

def ALU1: ProcResource<1>;
def ALU2: ProcResource<1>;

def WriteALU1: SchedWriteRes<[ALU1]> { let Latency = 1; }
def WriteALU2: SchedWriteRes<[ALU2]> { let Latency = 2; }

def : ItinRW<[WriteALU1, WriteALU2], [II_TEST]>

 From this example, we can access the latency information of MI with 
'getWriteLatencyEntry()' and the resource information of MI with 
'getWriteProcResBegin()'. At this point, I would like to find the 
related resource information with each latency information. But TableGen 
generates the 'WriteResourceID' of 'MCWriteLatencyEntry' when the 
'Write' is referenced by a 'ReadAdvance'. And the order of each 
information, which are resource and latency, is not same. Could you let 
me know whether it is possible to find the related resource information 
with each latency information or not?

Thanks,
JinGu Kang