[LLVMdev] De-pessimize ScalarEvolution's handling of nsw/nuw?

Jingyue Wu jingyue at google.com
Tue Dec 16 10:42:03 PST 2014

Thanks all of you for the input! I'm learning a lot about ScalarEvolution.

I understand, even in the NVPTX64 backend which doesn't natively support
i64 but uses 64-bit pointers, indvar widening can still be beneficial.
However, I chose to disable widening all together because it's hard to
evaluate the benefits of indvar widening before really trying it. For
instance, if we widen the indvar and found the widening doesn't improve LSR
(which runs as a backend IR pass), it's too late for us to rollback and the
widened indvar costs at least one extra 32-bit addition when being
incremented. That said, it seems hard to reach a uniformly optimal solution
here, so I'd probably leave the compiler as is and resort to source code


On Mon Dec 15 2014 at 11:38:42 PM Andrew Trick <atrick at apple.com> wrote:

> On Dec 4, 2014, at 1:39 PM, Jingyue Wu <jingyue at google.com> wrote:
> I was chasing down a performance regression on a CUDA benchmark compiled
> for the NVPTX64 backend, and found loop strength reduction is ineffective
> in the presence of sign extension. Here's a reduced test case:
> void foo(float *input, int n) {
>   for (int i = -n; i != n; ++i) {
>     baz(input[i + 5]);
>   }
> }
> I expect &input[i + 5] to be promoted to an indvar but it's not.
> The root cause of this misoptimization is that ScalarEvolution is
> pessimistic about tagging nsw/nuw to a SCEVAddExpr. This pessimization was
> introduced in http://llvm.org/viewvc/llvm-project?view=revision&revision=
> 145367. According to the comments there (http://llvm.org/docs/doxygen/
> html/ScalarEvolution_8cpp_source.html#l04087), ScalarEvolution does not
> apply an instruction's nsw/nuw flags to the corresponding SCEV expression.
> In the above example, &input[i + 5] corresponds to SCEV expression input
> + 4 * sext(i + 5). In order to promote &input[i + 5] to an indvar, we
> need to at least prove (i + 5) does not sign overflow so that we can
> reassociate the expression to (input + 5) + 4 * sext(i) which can be
> represented as a SCEVAddRecExpr. However, because ScalarEvolution doesn't
> apply sext to (i + 5), it cannot distribute sext(i + 5) to sext(i) + 5,
> and is thus unable to identify &input[i + 5] as a potential indvar.
> Side note: this issue kicked in after my recent recent change that
> disables induction variable widening for the NVPTX64 backend. This issue
> used to be alleviated (if any) by induction variable widening because there
> wouldn't be any sext if index i is already 64-bit.
> I wonder if the fix which disables applying nsw/nuw is too conservative.
> The comments in the source code say that ScalarEvolution does not apply
> an instruction's nsw/nuw flags to the corresponding SCEV expression because
> another non-control-equivalent instruction without nsw/nuw can be mapped to
> the same expression. If that's the only case we worried about, is a better
> fix to be not mapping instructions only differ in nsw/nuw to the same SCEV
> expression? That can be done by adding the wrapping flag of a SCEVAddExpr
> expression to the folding set that serves as the index of this expression
> for SCEV look-up.
> I followed this idea, and tried a preliminary change (
> http://reviews.llvm.org/differential/diff/16942/). It works fine so far:
> no transformation tests failed; some analysis tests failed but the new
> results seem better instead of incorrect. I wonder if I was just lucky on
> not breaking tests or it is the right way to go.
> SCEV is a system for computing algabreic equivalence. Control dependence
> has no place there. SCEV not an IR. The basic premise is that equivalent
> subexpressions will cancel. I don't understand how SCEV can fundamentally
> work if expressions are tagged with any kind of infomation derived from the
> IR.
> NSW/NUW flags currently don't change the way SCEV works because they are
> lazilly and conservativelly attached to the expression without affecting
> its identity. Even so, they still cause problems because they introduce
> nondeterminism w.r.t the order SCEVs are computed. They were just an
> expedient hack to support a corner case in C -- which turns out to be a
> case people care about. But we can't do much more with them within SCEV.
> Instead, the user of SCEV will need to reason about NSW/NUW. There has been
> a lot of discussion about that but I don't think anyone wants to take it on.
> I don't think LSR has a problem with your example. The incoming IR will
> have a sign-extend in the loop because that's what you asked for. It will
> treat the sign-extend as a use of the induction variable. The expression
> looks like this:
>   LSR Use: Kind=Basic, Offsets={0}, widest fixup type: i32
>     reg({(5 + (-1 * %n)),+,1}<nw><%for.body>)
> I take it that you want LSR to convert this from an array index into a
> pointer increment, like this:
>   LSR Use: Kind=Address of float, Offsets={0}, widest fixup type: float*
>     reg({(20 + (4 * (sext i32 (-1 * %n) to i64)) + %input),+,4}<%for.body>)
> To do that, you'll need to perform sign-extend elimination in indvars! I
> did think the NVPTX fix to disable IV widening was heavy-handed, but it's
> not my platform. It would certainly be easy to allow widening of simple
> cases of array[i+c]. I offered some suggestions in PR21148 I think.
> -Andy
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