[LLVMdev] Pseudo load and store instructions for AArch64

[Sergey Dmitrouk]

Hi Renato,

> I was thinking about this and I remember seeing a similar problem to
> yours in ARM. Something like:
> 
>   ldr r1, [sp, #20]
>   ldr r2, [sp, #24]
>   ldr r3, [sp, #28]
> 
> being reordered to:
> 
>   ldr r2, [sp, #24]
>   ldr r1, [sp, #20]
>   ldr r3, [sp, #28]

Well, it's a bit different.  What I'm trying to do is to turn

    ldp  x10, x11, [x9]     // load
    ldp x12, x9, [x9, #16]  // load
    stp  x10, x11, [x8]     // store
    mov  w0, wzr
    stp x12, x9, [x8, #16]  // store

into

    ldp  x10, x11, [x9]     // load
    stp  x10, x11, [x8]     // store
    ldp x12, x9, [x9, #16]  // load
    stp x12, x9, [x8, #16]  // store
    mov  w0, wzr

So "load" + "load" and "store" + "store" are already fine, I need paired
operations to be properly interleaved and adjacent.  It should result
in better performance even though machine instruction scheduler thinks
differently.

> fixing loads and stores, maybe you could add a similar thing to
> AArch64?

AArch64LoadStoreOptimizer already exists, but I'll try to add
instruction reordering to it, I saw some code for moving instructions in
ARMLoadStoreOptimizer.  Saleem suggested something similar.

> That'd have the benefit of not polluting the table-gen files, and
> could be turned on via a flag, on demand, that only after heavily
> tested, could be turned on by default.

I'd prefer that as well.  Pseudo instructions was the last resort as I
was out of options.

Thanks for your help.

Regards,
Sergey