[LLVMdev] Pseudo load and store instructions for AArch64

[Sergey Dmitrouk]

Saleem,

> we generate a bundle (similar to the VLIW concept)

Is it possible to specify that a bundle uses a couple of registers
internally?  Which are not input, not output registers, but are rather
temporaries.  If the answer is no, then it won't work anyway.

> Although, that approach could work, it feels like updating the
> LoadStoreOptimizer to deal with the particular case may be a cleaner
> approach.

Thanks!  I didn't notice that load/store optimizer is executed *after*
machine instructions scheduler, which should allow to move some of
instructions.

Regards,
Sergey

On Tue, Aug 26, 2014 at 07:29:32PM -0700, Saleem Abdulrasool wrote:
>    On Fri, Aug 22, 2014 at 6:01 AM, Renato Golin <renato.golin at linaro.org>
>    wrote:
> 
>      On 22 August 2014 13:44, Sergey Dmitrouk <sdmitrouk at accesssoftek.com>
>      wrote:
>      > This is the only way I found to stop Machine Instruction Scheduler
>      from
>      > reordering load and store instructions.
> 
>      I see. Saleem (cc'd) worked on a similar thing for ARM's movh/movt for
>      Windows, which also didn't like the reordering. Maybe he can help you.
> 
>    Sorry, Ive been a bit busy at work :-(.
>    For Windows on ARM, the movw/movt relocations need to be contiguous. A In
>    order to accommodate that, we generate a bundle (similar to the VLIW
>    concept) to treat the pair as a single scheduling entity.
>    Although, that approach could work, it feels like updating the
>    LoadStoreOptimizer to deal with the particular case may be a cleaner
>    approach.
>    A 
> 
>      cheers,
>      --renato
> 
>    --
>    Saleem Abdulrasool
>    compnerd (at) compnerd (dot) org