[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?

[Akira Hatanaka]

On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote:

> Hi, Akira,
>
> I found you maintain mips MipsSchedule.td. does it correct? in
> MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
> ByPass info out there.
> are you sure this reflects the real R4xxx/R5xxx processors.
>
> why IILoad uses funcition unit ALU?
> InstrItinData<IILoad             , [InstrStage<3,  [ALU]>]>
>
>
This means IILoad instructions use resource ALU for three cycles. I don't
remember why only two functional units (ALU and IMULDIV) are defined and
used in this .td file, but this would be incorrect if load instructions did
not have any resource conflicts with other ALU instructions on your target.


>
> for my previous question, I have new input after reading the code.
> pre-RA-sched is derived from ScheduleDAGSNodes, but post-RA-sched and
> mi-sched are both derived from ScheduleDAGInstrs.that means pre-RA-sched
> schedules SDNodes. post-RA-sched schedules MIs.
>
> from -debug-pass=Structure, we can see that the order is "mi-sched"==>
> RegisterAllocation==>post-RA TD.
>
>       Simple Register Coalescing
>       Machine Instruction Scheduler
>       Machine Block Frequency Analysis
> ...
>       Greedy Register Allocator
>       Virtual Register Rewriter
> ...
>       Post RA top-down list latency scheduler
>       Analyze Machine Code For Garbage Collection
> ...
>
>
> for my testcase, I found -enable-misched is helpful for ARM, they reduce
> stall numbers from 205 to 160. however, mips is adverse impact. the stall
> number increases from 554 to  560. this doesn't make any sense.
>
>
I don't know for sure why stalls increase. In my experience, both pre-RA
and post-RA improve performance when I run the compiled executables on a
mips board. But as I said in my previous email, the model in
MipsSchedule.td is just a generic one, so it's possible that it isn't
generating efficient code for your target.



> thanks
> --lx
>
>
>
> On Fri, Sep 20, 2013 at 10:50 AM, Liu Xin <navy.xliu at gmail.com> wrote:
>
>> Akira,
>>
>> Thanks you for response.
>>
>> I understand Post-RA schedule make uses of scoreboardHazardRecognizer.
>> But I found mips codes are good enough by default. basically, I can not
>> easily eyeball any bubbles.
>> I don't understand how they can do that without post-RA-sched.
>> pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little
>> information and they can only schedule node in topology order. It assumes
>> any SU is one cycle delay.  I don't think pre-ra-sched consider any
>> pipeline details.
>>
>> thanks,
>> --lx
>>
>>
>>
>> On Fri, Sep 20, 2013 at 5:39 AM, Akira Hatanaka <ahatanak at gmail.com>wrote:
>>
>>> Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so
>>> you will have to compile with -O3.
>>>
>>> You can also invoke the MI (pre-RA) scheduler with llc option
>>> "-enable-misched". As you have pointed out, the post-isel scheduler is
>>> mandatory, and therefore you don't have to give any command line options.
>>>
>>> Currently, mips has only one generic scheduling itinerary model in
>>> MipsSchedule.td that is not tailored to any specific core, so you might
>>> have to tweak it to have the scheduler generate efficient code for your
>>> target.
>>>
>>>
>>> On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>>>
>>>> Hi, LLVM,
>>>>
>>>> I found LLVM codegen has 3 passes for instruction scheduling:
>>>>
>>>> 1) pre-ra sched
>>>> 2) post-ra sched
>>>> 3) mi sched.
>>>>
>>>> for RISC machines, there are data hazard cases appear only after
>>>> Register Allocation(RA).  for example, $t0 is used immediately after
>>>> writing(RAW):
>>>>
>>>> ld $t0, MEM
>>>> add $t2, $t0, $0
>>>>
>>>> There may be one or more stall in pipeline. Instruction scheduler can
>>>> detect this kinds of conflict and insert other instructions to avoid
>>>> pipeline bubble. I think this work only can be done after RA.  If so,
>>>> what's the purpose for 1). I found 1) is mandatory  and 2/3) are optional.
>>>> Further, at least one target enable pre-RA-sched with harzardRecognizer.
>>>> Does it really work out? you can resolve data hazard using pre-RA-sched
>>>> only?
>>>>
>>>> thanks,
>>>> --lx
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> _______________________________________________
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>>>>
>>>>
>>>
>>
>
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