[LLVMdev] prevents instruction-scheduler from interfereing instruction pair

[Liu Xin]

Hi, LLVM list,

I am using Post-RA scheduler to reorder instructions. by now, it's helpful
for our processor but I meet a trouble. In our ISA, we have fixed
instruction pairs. that is to say, our cpu must see instrA right before
instrB. it's not acceptable to have any instruction between them. we call
it an instruction pair.

The problem is I am not aware of describing this kind of constraint in TD
or cpp code. Post-RA scheduler may insert an instruction between
instruction pair. Does any other ISA have similar constraints and how do
you solve this problem? I know newer llvm has switched to MI-sched. I
observed this same issue.

on my side, I defined some intrinsics which represent instruction pairs.
Instruction-scheduler can not guarantee they appear consecutive in final
instructions.

thanks,
--lx
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