[LLVMdev] Instrudtion operand definition question

Steve Barnett barnett at coherentlogix.com
Fri May 31 07:07:36 PDT 2013


I am in the process if evaluating whether the LLVM code generator is a workable solution for Coherent Logix next generation of CPU.

I am struggling with how to practically define the instruction set with TableGen. I believe that defining a different instruction for each type of operand would result in a number of instruction definitions that would be impractical.

A unique feature of our chip is that it is memory based. Most arithmetic is done in a typical way ($a = add $b, $c). The difference is that the result ($a) can be a register or memory address and the operands ($b and $c) can be a register, a constant or a memory address. There is also an accumulator register and status bits written. The result can also be %null meaning that the result is only written to the accumulator. Defining all the possible operand formats in separate instruction definitions would result in a huge number of instructions.

The addressing modes are defined like this:

  offset[%base_reg, %index_reg]

One, two or all three can be defined and the offset can be a relocatable symbol or a signed int.

Memory operands need not be introduced until just before register allocation (maybe they couldn't be?).

Any suggestions on how to attack this problem would be greatly appreciated.


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