[LLVMdev] Activating MIPS Code Emitter.
pluck90 at hotmail.com
Thu May 30 10:12:26 PDT 2013
I need to represent each instruction with its (32-bit) binary encoding, and I reached to a conclusion that I could get the encoding through the MipsCodeEmitter. What I’m trying to do exactly is write a scheduler which tries to minimize the switching activity between the scheduled instructions in each basic block. One way to do that is by representing each instruction with its complete binary encoding, which will be available after the register allocation.
Thanks for the reply!
From: Jim Grosbach
Sent: Thursday, May 30, 2013 7:55 PM
To: Jafar J
Cc: llvmdev at cs.uiuc.edu ; Mailing List
Subject: Re: [LLVMdev] Activating MIPS Code Emitter.
What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler.
On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote:
Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is this the way to activate the mipsCodeEmitter during PostRA Scheduler or am I missing something here.
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