[LLVMdev] Error on VSELECT Dagcombiner with some architecture

jingu kang jaykang10 at gmail.com
Tue May 28 08:18:02 PDT 2013

Hi all,

I met the error while compiling the code with vector type with some
architecture. IR is as following.

  %cmp = icmp sgt <3 x i8> %x, zeroinitializer
  %sub = sub <3 x i8> zeroinitializer, %x
  %cond = select <3 x i1> %cmp, <3 x i8> %x, <3 x i8> %sub

'select' IR is converted to 'vselect' dag and is combined to 'sra (X,
size(X)-1); xor (add (X, Y), Y)'. There is a problem here. If the target
support i8 type as promote integer to make size(X), size(X) has i32 type.
and then type legalize pass do widening the vector like this.

  v4i8 = BUILD_VECTOR 0x99d90a8: i32 = Constant<7> [ID=-3], 0x99d90a8: i32
= Constant<7> [ID=-3], 0x99d90a8: i32 = Constant<7> [ID=-3], 0x9a6c6c8: i8
= undef

In the end, type legalizer generates a error like this "Operands must all
have the same type"'. I tested this code with ARM and MIPS.

Target specific dag combiner functions runs after default dag combiner
functions so I feel it's not possible to support target specific dag
combiner function of vselect to fix this problem. Should I check the sra?
What do you think about this? In order to remove this error, I just removed
the vselect dag combiner function.

JinGu Kang
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