[LLVMdev] Definition of RegisterClass for load instruction in Thumb2

Junbum Lim junbums at gmail.com
Thu May 23 08:14:36 PDT 2013


I have a question about the definitions of t2LDRSB and t2LDRSB_PRE in ARMInstrThumb2.td :

I was aware that the definitions of  target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE.  While t2LDRSB  uses rGPR,  t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?
defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
                      rGPR, UnOpFrag<(sextloadi8  node:$Src)>>;


def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
                            (ins t2addrmode_imm8:$addr),
                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
                            []> {
  let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";

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