[LLVMdev] Types vs. register classes in instruction patterns -- effect on FastISel

Bill Schmidt wschmidt at linux.vnet.ibm.com
Fri May 17 14:04:24 PDT 2013


In http://llvm.org/viewvc/llvm-project?view=revision&revision=177889 and
http://llvm.org/viewvc/llvm-project?view=revision&revision=177890 (along
with some follow-up patches) the PowerPC back end was changed to use
types instead of register classes in instruction patterns.  This matched
similar changes that Jakob made for Sparc in r177835.

I've recently come across an unpleasant side-effect of this change.  I
started looking at implementing FastISel for PPC64, and discovered that
practically all of our patterns were rejected when looking for simple
patterns eligible for FastEmit_*.  Stepping through the tablegen code
showed that we were rejecting them precisely because the patterns now
contain value types instead of register classes (FastISelEmitter.cpp,
lines 253ff.):

      // For now, the only other thing we accept is register operands.
      const CodeGenRegisterClass *RC = 0;
      if (OpLeafRec->isSubClassOf("RegisterOperand"))
        OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
      if (OpLeafRec->isSubClassOf("RegisterClass"))
        RC = &Target.getRegisterClass(OpLeafRec);
      else if (OpLeafRec->isSubClassOf("Register"))
        RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
        return false;

What's the proper thing to do here?  If we can map a ValueType to a
register class, then we'd be ok.  I don't immediately see an interface
that will do this (indeed, I guess I'm not certain that's guaranteed to
be a 1-1 mapping).

This wasn't noticed previously on Sparc or PowerPC since neither has had
a FastISel implementation yet.  Thoughts?


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