[LLVMdev] Tracking down a SELECT expansion to predicated moves

Jim Grosbach grosbach at apple.com
Mon May 13 13:24:31 PDT 2013


Hi Dan,

It’s probably legalization.

-Jim

On May 13, 2013, at 12:35 PM, Dan <westdac at gmail.com> wrote:

> 
> 
> I've inherited some target code, but there is no SELECT lowering in my target.  But somewhere/somehow SELECT is being transformed into a predicated move.  I've traced SELECT everywhere in Codegen/SelectionDAG.
> 
> Any ideas on tracking this down to the point in Codegen lowering/dag-conversion to a predicated series? Again, I do not have a lowering rule in my target for SELECT.
> 
> If I do a IR DUMP Before Expand ISel Pseudo-instruction, I will get a CMOV listed in the code (shown below).  But I cannot track down how/where the CMOV is being generated from the SELECT.
> 
> Help?
> 
> Here's the basic code and llvm IR:
> 
> #include <stdio.h>
> 
> int a = 0;
> int b = 0;
> 
> int main() {
>   a = (b > 0) ? 23 : 8;
>   return 0;
> }
> 
> 
> ; ModuleID = 'try.c'
> 
> @a = global i32 0, align 4
> @b = global i32 0, align 4
> 
> define i32 @main() nounwind {
> entry:
>   %0 = load i32* @b, align 4
>   %cmp = icmp sgt i32 %0, 0
>   %cond = select i1 %cmp, i32 23, i32 8
>   store i32 %cond, i32* @a, align 4
>   ret i32 0
> }
> 
> # *** IR Dump Before Expand ISel Pseudo-instructions ***:
> # Machine code for function main: SSA
> Function Live Outs: %r8
> 
> BB#0: derived from LLVM BB %entry
>         %vreg0<def> = MOVL_GA <ga:@b>; GR:%vreg0
>         %vreg1<def> = LDSHri %vreg0<kill>, 0; mem:LD4[@b] GR:%vreg1,%vreg0
>         %vreg2<def> = MOVIMM21 0; GR:%vreg2
>         %vreg3<def> = CMPGT %vreg1<kill>, %vreg2; PR:%vreg3 GR:%vreg1,%vreg2
>         %vreg4<def> = MOVIMM21 8; GR:%vreg4
>         %vreg5<def> = MOV %vreg4<kill>; GR:%vreg5,%vreg4
>         %vreg6<def> = MOVIMM21 23; GR:%vreg6
>         %vreg7<def,tied1> = CMOV %vreg5<tied0>, %vreg6<kill>, %vreg3<kill>; GR:%vreg7,%vreg5,%vreg6 PR:%vreg3
>         %vreg8<def> = MOVL_GA <ga:@a>; GR:%vreg8
>         STHri %vreg8<kill>, 0, %vreg7<kill>; mem:ST4[@a] GR:%vreg8,%vreg7
>         %r8<def> = COPY %vreg2; GR:%vreg2
>         RET %r31<imp-use>
> 
> # End machine code for function main.
> 
> 
> 
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