[LLVMdev] Predicated Vector Operations

dag at cray.com dag at cray.com
Fri May 10 09:53:39 PDT 2013

Jeff Bush <jeffbush001 at gmail.com> writes:

> Ah, I think I get it now.  This was mentioned earlier in the thread,
> but it didn't click at the time. It sounds like I can do instruction
> selection with a pattern like (omitting selection of the sources):
> let Constraints = "$dst = $oldvalue" in {
>     def MASKEDARITH : MyInstruction<
>         (outs VectorReg:$dst),
>         (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
> VectorReg:$oldvalue),
>         "add $dst {$mask}, $src1, $src2",
>         [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1,
> v16i32:$src2), v16i32:$oldvalue))]>;
> }

Ok, but where does $oldvalue come from?  That is the trickty part as far
as I can see and is why this isn't quite the same as handling
two-address instructions.

I agree that the pattern itself is straightforward.  It's bascially what
I've written here.


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