[LLVMdev] Predicated Vector Operations

dag at cray.com dag at cray.com
Wed May 8 13:53:53 PDT 2013

Nadav Rotem <nrotem at apple.com> writes:

> Most passes won't have to handle the load/store intrinsics because
> they will look like a regular function calls that read/write from
> memory. We don't need to change Reg2Mem or other passes that really
> can't do anything about masked memory operations. On the other hand,
> If we do change the Load/Store instruction we will have to review all
> of our existing optimizations. For example, some optimizations assume
> that a store instruction actually writes and invalidates the memory
> location. However, this assumption is incorrect if we are using a
> mask. 

Yes, this makes sense.

What happens if we add a new first-class IR instruction?  I suppose
passes that have visitor-like behavior will have to add code to
handle it, but that code could simply treat it like an intrinsic,
an unknown black box.

I suppose that fact that intrinsics can be attributed so passes
automatically assume they read and/or write memory is an advantage in
that nothing special has to be done to passes to make them handle it

Just thinking out loud.  There's something not quite sitting right with
me about making masked load and store be intrinsics but I'm not sure
what it is.  It's likely due to not completely understanding the
semantics of generic intrinsics.

I would like to know how people determine whether a new instruction-like
IR change should take the form of an intrinsics or a first-class


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