[LLVMdev] Predicated Vector Operations

Jeff Bush jeffbush001 at gmail.com
Mon May 6 18:45:11 PDT 2013

I'm trying to understand how predicated/masked instructions can be
generated in llvm, specifically an instruction where a set bit in the mask
will write the new result into the corresponding vector lane in the
destination and a clear bit will cause the lane in the destination to
remain what it was before the instruction executed.

I've seen a few places that suggest 'select' is the proper way to implement
predication.  I believe the predicated form cannot be explicitly expressed
in LLVM asm, because it is SSA.  It can be done implicitly:

  %sum = add <16 x i32> %x, %y
%newvalue = select <16 x i1> %mask, <16 x i32> %sum, <16 x i32> %oldvalue
The issue becomes how to match the instruction form above in a TableGen
pattern.  In order for this to emit a masked instruction, %newvalue and
%oldvalue must be assigned to same physical register (I'm assuming an
instruction like 'add %r0{%m0} %r1 %r2') However, I don't think there is
even a notion of physical registers at the point that instruction selection
is performed and the virtual registers will be different because everything
is still in SSA form.

I suspect I'm missing something fundamental.
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