[LLVMdev] Handling Masked Vector Operations

Duncan Sands baldrick at free.fr
Fri May 3 01:10:11 PDT 2013

Hi David,

On 02/05/13 17:57, dag at cray.com wrote:
> We're looking at how to handle masked vector operations in architectures
> like Knight's Corner.  In our case, we have to translate from a fully
> vectorized IR that has mask support to llvm IR which does not have mask
> support.
> For non-trapping instructions this is fairly straightforward:
> ; Input
> t1 = add t2, t3, mask
> ; llvm IR -- assuming we want zeros in the false positions, which is not
> ; always the case
> tt = add t2, t3
> t1 = select mask, tt, 0

there seems to be a plan to get rid of the select instruction and just use
branches and phi nodes instead.  Amongst other things this requires boosting
the power of codegen so that branches+phi nodes can be turned into cmov or
whatever when appropriate.

> It's easy enough to write a TableGen pattern to match add+select and
> emit a masked instruction.  Alternative, we can always resort to manual
> lowering (ugh).
> For trapping operations this is problematic.  Take a load.  Here's the
> same attempt with a load:
> tt = load [addr]
> t1 = select mask, tt, 0

This would not be problematic at the IR level if it was done by branching to
one of two basic blocks based on the condition, and doing the load in the
appropriate basic block.  Codegen would however need to become powerful enough
to turn this construct into your target's predicated load.

Ciao, Duncan.

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