[LLVMdev] Types in TableGen instruction selection patterns

[Sebastian Pop]

Sebastian Pop wrote:
> same mechanism could be useful. It would be nice to be able to write this:
> 
>   def insn : Inst<(outs i32:$dst), (ins i32:$src1, i32:$src2),
>             "some assembler",
>             [(set $dst, (Op $src1, $src2))]>;

>From the PPC changes, I see that this is already possible under a slightly
different form:

   def FSUBS : AForm_2<59, 20,
                       (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
                       "fsubs $FRT, $FRA, $FRB", FPGeneral,
-                      [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
+                      [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;


Sebastian
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