[LLVMdev] Types in TableGen instruction selection patterns

Sebastian Pop spop at codeaurora.org
Mon Mar 25 12:50:46 PDT 2013

Jakob Stoklund Olesen wrote:
> I have updated TableGen to support a new format for instruction selection patterns.
> Before:
>   def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
> After:
>   def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
> Since the pattern matching happens on a DAG with type labels, not register
> classes, I think it makes more sense to specify types directly on the input
> patterns.

Does it make sense to also make this mechanism available in the definition of
instructions' matching code [], this is the only other place I see where this
same mechanism could be useful. It would be nice to be able to write this:

  def insn : Inst<(outs i32:$dst), (ins i32:$src1, i32:$src2),
            "some assembler",
            [(set $dst, (Op $src1, $src2))]>;

> The new syntax also helps avoid the problem where TableGen emits
> lots of type inference errors when multiple types are added to a register
> class.

This is nice!  Thanks for the cleanup!

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