[LLVMdev] About the partial update clearence / dependency breaking mechanism
Jakob Stoklund Olesen
stoklund at 2pi.dk
Mon Mar 25 09:42:39 PDT 2013
On Mar 25, 2013, at 5:02 AM, Silviu Baranga <silbar01 at arm.com> wrote:
> I am currently looking into the advantages of using the
> partial update clearance / dependency breaking mechanism
> for some ARM cores.
> It seems that the ARM specific code for this will always
> return a clearance of 0 for VLD1LNd32 because of the following
> code in getPartialRegUpdateClearance:
>> if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
>> return 0;
> so essentially VLD1LNd32 (and potentially other instruction)
> will never be affected by this. Was this intended or is there
> a bug here?
> I'm confused why the dependency breaking code is correct.
> Why would the dependency breaking mechanism apply only
> when the register is dead?
It's breaking *false* dependencies.
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