[LLVMdev] hazard scheduling nodes
jonas.paulsson at ericsson.com
Tue Mar 12 03:43:33 PDT 2013
The thing is that I was trying to build a sched graph in other places than these two standard scheduling passes. For instance, in pre-emit. I would like to reschedule a basic block on my vliw target just before assembly emission.
I tried to add SUnits for hazards in an experiment, but this gave very weird errors... even while allocating extra space in SUnits vector. For some function, I could not even build the sched-graph, so that's when I mailed you. My question is still whether it is possible to use the scheduler classes at an arbitrary point, and what the pitfalls might be...
From: Andrew Trick [mailto:atrick at apple.com]
Sent: Saturday, March 09, 2013 3:05 AM
To: Jonas Paulsson
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] hazard scheduling nodes
On Feb 21, 2013, at 9:11 AM, Jonas Paulsson <jonas.paulsson at ericsson.com<mailto:jonas.paulsson at ericsson.com>> wrote:
I am trying to add Hazard scheduling nodes after buildSchedGraph(), with a scheduler derived from ScheduleDAGInstrs. I get weird errors, so I wonder what I am doing wrong?
What I am doing right now is:
I have a created MI with opcode HAZARD that does not have parent, and I greate a SUnit(HazardMI). I use this one HazardMI for all hazard nodes.
I remove all edges using removePred.
I insert edges between Node -> hazardNode -> pred.
What is there to think about in this approach? I must be missing some detail...
Any help is appreciated,
Jonas, I'm sorry I forgot to respond to this. Hopefully you figured out how to debug it. I'm not sure if you're using the MachineScheduler pass or PostRAScheduler.
For MachineScheduler, use -view-misched-dags and -debug-only=misched.
For PostRA: -debug-only=post-RA-sched.
Modifying the DAG edges is tricky to get right. But removePred() and addPred() are the basic primitives...
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