[LLVMdev] Custom Lowering of ARM zero-extending loads

Giang Hoang ghoang84 at gmail.com
Mon Mar 4 13:14:54 PST 2013


For my research, I need to reshape the current ARM backend to support
armv2a.  Zero-extend half word load (ldrh) is not supported by armv2a, so I
need to make the code generation to not generate ldrh instructions.  I want
to replace all those instances with a 32-bit load (ldr) and then and the
result with 0xffff to mask out the upper bits.

These are the modifications that I have made to accomplish that:

1.  Register the ZEXTLOAD for custom lowering:

setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);

2.  Implement a custom lowering function:

static SDValue LowerExtLoad(SDValue Op, SelectionDAG &DAG) {
  LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode());
  ISD::LoadExtType ExtType = LD->getExtensionType();

  if (LD->getExtensionType() == ISD::ZEXTLOAD) {
    DEBUG(errs() << "ZEXTLOAD\n");
    SDValue Chain = LD->getChain();
    SDValue Ptr = LD->getBasePtr();
    DebugLoc dl = Op.getNode()->getDebugLoc();
    SDValue LdResult = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32,
                                      Chain, Ptr, LD->getPointerInfo(),
                                      LD->isVolatile(), LD->isNonTemporal(),
    Chain = LdResult.getValue(1);
    SDValue Mask = DAG.getConstant(0x1, MVT::i32);

    DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 0), LdResult);
    DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), Chain);
    //return DAG.getNode(ISD::AND, dl, MVT::i32, Op, Mask);


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