[LLVMdev] Rematerialization and spilling

[Steve Montgomery]

I'm working on an out-of-tree target and am having some problems with rematerialization and spilling.

The target's load and store instructions affect the condition code register (CCR). Describing this in the InstrInfo.td file using Defs = [CCR] certainly prevents spills and fills from being inserted where they might clobber CCR but it also prevents the load instruction from being rematerialized because it defines a physical register (TargetInstrInfo::isReallyTriviallyReMaterializableGeneric()).

I've tried to take the approach that's used by the X86 target, in which instructions _are_ trivially rematerializable even if they implicitly define the condition code (EFLAGS) but must take care not to clobber EFLAGS if it's live at the point where the instruction is rematerialized. However, because my original load instruction implicitly defines CCR, and this isn't marked as dead, the instruction can't be deleted so the destination register is spilled anyway.

I thought maybe I should pretend that load and store don't implicitly define CCR but then I'd need to prevent spill / fill when CCR is live, e.g. between compare instructions and conditional branch instructions. Would machine instruction bundles be the right way to do this?

I'd be grateful for any advice.