[LLVMdev] [PATCH] x86: disambiguate unqualified btr, bts

Eric Christopher echristo at gmail.com
Wed Jul 10 14:30:08 PDT 2013

On Wed, Jul 10, 2013 at 2:08 PM, Ramkumar Ramachandra
<artagnon at gmail.com> wrote:
> Jim Grosbach wrote:
>> To say that another way, is the assembler correctly diagnosing a previously
>> unnoticed problem in the project source code, or is the assembler not
>> behaving correctly according the the documented Intel assembly mnemonics?
> Where are the authoritative instruction set pages?  If such a thing
> were readily available, why are there gaps in the current
> implementation?  A quick Googling gets me [1], but I can't say it's
> authoritative.  What's important is that there certainly are
> architectures where btr/bts are valid instructions, and they must be
> supported.  btr/bts are certainly not invalid instructions that we're
> bending over backwards to support, because linux.git/gas works with
> them.
> [1]: http://web.itu.edu.tr/kesgin/mul06/intel/index.html
> _

The correct answer here is "Vol 2a of the Intel Reference Manual
available off of the Intel website".

As far as whether or not we should support the instructions with a
lack of length mnemonic, I'm going to step back away from the
discussion. The Intel manuals support Intel syntax (which we also
support) which necessarily doesn't have length encodings for most
instructions, but AT&T syntax which gas uses (and llvm supports as
well) often has length specifiers for instructions.


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