[LLVMdev] Tablegen problem populating TSFlags

Joe Matarazzo joe.matarazzo at gmail.com
Wed Jan 30 16:17:02 PST 2013

It seems like this code should work with Tablegen, but it generates the error:

"error:Invalid TSFlags bit in ADD"

Here's the code:
include "llvm/Target/Target.td"

def MyInstrInfo : InstrInfo;

def MyTarget : Target {
  // Information about the instructions...
  let InstructionSet = MyInstrInfo;

def r1 : Register<"r1"> { let Namespace = "Test"; }

def RC1 : RegisterClass<"Test", [i8], 8, (add r1)>;

class BitField<bits<2> x> {
  bits<2> Val = x;

def VALUE_0 : BitField<0>;
def VALUE_1 : BitField<1>;
def VALUE_2 : BitField<2>;
def VALUE_3 : BitField<3>;

class MyInstruction<dag outs, dag ins, string asmstr, list<dag>
pattern> : Instruction
  let Namespace = "Test";

  let OutOperandList    = outs;
  let InOperandList     = ins;
  let AsmString         = asmstr;
  let Pattern           = pattern;

  bit Choice            = 1;
  BitField foo          = !if(Choice, VALUE_1, VALUE_3);

  let TSFlags{1-0}      = foo.Val;

def ADD : MyInstruction<(outs RC1:$dst), (ins RC1:$r0, RC1:$r1), "add
$r0,$r1", [(set RC1:$dst, (add RC1:$r0, RC1:$r1))]>;


Based on some initial debug it seems like it's getting confused with
an extra level of indirection resolving the VarBits records for the
foo variable. I thought I would ask the experts before digging

The command line I used with the above testcase is

llvm-tblgen.exe -gen-instr-info -I C:\LLVM\llvm\lib\Target -I
C:\LLVM\llvm\include test.td -o foo.tmp


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